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Applying the DLX1414 Intelligent Display(R) Products Appnote 15
This application note is intended to serve as a design and application guide for users of the DLX1414 alphanumeric Intelligent Display. The information presented covers device electrical description and operation, considerations for general circuit design, and interfacing the DLX1414 to microprocessors. Electrical & Mechanical Description The internal electronics of the Intelligent Display eliminates all the traditional difficulties of using multi-digit light emitting displays (decoding, drivers and multiplexing). The Intelligent DisFigure 1. Block Diagram-DLX1414
D isplay R ow s 0 to 6 3 R o w C o n t r o l Log i c & Ro w Dri vers 2 1 0 C olu mns 0 to 19
play also provides internal memory for the four digits. With this approach the user can asynchronously address one of four digits and load new data without regard to the LED multiplex timing. Figure 1 is a block diagram of the DLX1414. The device consists of four (5x7) LED arrays and a single CMOS integrated chip. The IC chip contains the column drivers and row drivers, 128 character ROM, four word x7 bit Random Access Memory, oscillator for multiplexing, multiplex counter/decoder, cursor memory, address decoder, and miscellaneous control logic.
OSC
/128 Counter
/7 Counter
Timing and C ontrol Logic
Row D ecoder Column Decoder ROM 128x35 Bit ASCII C haracter D ecode 4480 Bits C olumn D ata D isplay O utput Logic
D6 D5 D4 D3 D2 D1 D0
7 B i t A SC II C ode RAM Me mory 4 x7 Bi t
WR A0 A1
Wri t e A d d re ss De co d er
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
Latc hes
RAM Read Logic
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Figure 2. Top view and pin outs
12 11 10 9 87
Table 1. Electrical inputs to the DLX1414 VCC GND D0-D6 Positive supply +5 V Ground Data lines The seven data input lines are designed to accept the first 128 ASCII characters. See Figure 3 for the character set. Address Lines The address determines the digit position to which the data will be written. Address order is right to left for positive-true logic. Write (Active Low) Data and address to be loaded must be present and stable before and after the trailing edge of write. (See data sheet for timing info).
digit digit digit digit 3 2 1 0
1 2 3 4 5 6
A0, A1
Pin 1 2 3 4 5 6
Function D5 Data Input D4 Data Input WR Write A1 Digit Select A0 Digit Select VCC
Pin 7 8 9 10 11 12
Function GND D0 Data Input (LSB) D1 Data Input D2 Data Input D3 Data Input D6 Data Input (MSB) Operation WR
Packaging Packaging consists of an injection-molded plastic lens which covers five of the six "faces." The assembled and tested substrate is placed within the shell and the entire assembly is then filled with a waterclear IC-grade epoxy. This yields a very rugged part which is quite impervious to moisture, shock and vibration. Although not "hermetic, the device will easily withstand total immersion in water/detergent solutions. Figure 3. Character set-DLX1414
D0 D1 D2 D3 D6 D5 D4 HEX ASCII CODE 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 A 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 1 1 E 1 1 1 1 F
Multiplexed display systems sequentially read and display data from a memory device. In synchronous systems, control circuitry must compare the location of data to be read to the location or position of new data to be stored or displayed, i.e., synchronize before a Write can be done. This can be slow and cumbersome. Data entry in Intelligent Displays is asynchronous and may be done in any random order. Loading data is similar to writing into a RAM. Each digit has its own memory location and will display until replaced by another code. The waveforms in Figure 4 demonstrate the relationships of the signals required to generate a Write cycle. (Check individual data sheet for minimum values.) As can be seen from the waveforms, all signals are referenced from the rising or trailing edge of Write. General Design Considerations Using positive true logic, address order is from right to left. For left to right address order, use the ones complement or simple inversion of the addresses. Figure 4. Write cycle waveform
tAS
A0-A1 D0-D6 4V 2V 0V 4V 2V 0V 4V 2V 0V tAH
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
tDS tW
tDH
1
1
0
6
1
1
1
7
WR
1. High=1 level. 2. Low=0 level. 3. Upon power up, device will initialize in a random state.
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
Appnote 15
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May 31, 2000-12
When using the DLX1414 on a separate display board with more than 6 inches of cable length, it may be necessary to buffer all inputs. This is most easily achieved with Hex non-inverting buffers such as the 74365. The object is to prevent transient current in the protection diodes. The buffers should be located on the display board near the displays. Local power supply bypass capacitors are also needed in many cases. These should be 6 or 10 volt, tantalum type with 10 F or greater capacitance. Low internal resistance is important due to current steps which result from the internal multiplexing of the displays. If small wire cables are used, good engineering practice is to calculate the wire resistance of the ground plus the +5 volt wires. More than 0.1 volt drop, (at 25 mA per digit worst case) should be avoided, since this loss is in addition to any inaccuracies or load regulation limitations of the power supply. The 5-volt power supply for the displays should be the same one supplying VCC to all logic devices which drive the display devices. If a separate supply must be used, then local buffers using hex, non-inverting gates should be used on all inputs and these buffers should be powered from the display power supply. This precaution is to avoid logic inputs higher than display VCC during power up or line transients. Interfacing the DLX1414 A general and straightforward interface circuit is shown in Figure 6. This scheme can easily interface to LP systems or any other systems which can provide the seven data lines, appropriate address and control lines. The DLX1414 does not have a chip enable input; therefore each display in a system requires its Write pulse be gated with appropriate address signals. Figure 7a shows the use of a 74154 decoder (4 lines to 16 lines) for up to a 64 character display. Using the G1 input for display select (address select in a memory mapped system) and the G2 input to gate the Write signal. Another approach (Figure 7b and 7c) which minimizes logic for a 16 or 32 digit display takes advantage of decoding scheme of the 7442 decoder. Parallel l/O The parallel l/O device of a microprocessor can be connected easily to the circuit in Figure 6. One eight bit output port can provide the seven input data bits. Another eight bit output port can contain the address and control signals.
Figure 5. Data loading table
Address WR A1 A0 D6 H L L L L L L L X L L H H L H - X L H L H L L - X H H H H H H - Data Input D5 D4 D3 D2 X L L L L L L - X L L L L L L - X L L L L L H - X L L L H H L - D1 D0 X L H H L L H - X H L H L H H - D i gi t 3 NC NC NC NC D D D D i gi t 2 NC NC L C C C K Digit 1 NC NC B B B B B Digit 0 NC A A A A E E
See Character Set NC=No change
X=Don't care
Figure 6. General interface circuit
Vcc GND Display Display Display Display D8 D7 D4 D3 D0 D15 D12 D11
2/
D0-A6 A0 A1 Digit Select D WR C A3 B A2 A
WR
WR
WR
WR
Decoder
Figure 7. Gating the write pulse
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
7a.
Di spl a y Se l e c t WR A2 A3 A4 A5
G1 G2 A B C D 74154
to W R of Disp lay
7 b.
Di gi t Se l e c t WR A3 A2
9 8 7 6 C 7442 5 4 B 3 2 A 1 0 D 9 8 7 6 C 5 7 44 2 4 B 3 2 A 1 0 D
Un u se d
to W R o f Disp lay
7c.
Di gi t Se l e c t WR A4 A3 A2
Un u se d
to W R o f Disp lay
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
Appnote 15
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May 31, 2000-12
Figure 8. 16-digit parallel I/O
Vcc GND D0-D6 2 Control 8080 P System Data 0 1 2 3 4 5 6 7 Display Display Display Display D15 D0 WR WR WR WR
I/O or Memory Mapped Addressing Some designers may wish to avoid the additional cost of a parallel l/O in their system. Structuring the addressing architecture for the DLX1414 to look like a set of peripheral or output devices (I/O mapped) or RAMs and ROMs (memory mapped), is very easy. Figure 9 shows the simplicity of interfacing to microprocessors, such as 8080, Z80 and 6502 as examples. The interface with the 6800 microprocessor in Figure 10 illustrates the need for designers to check the timing requirements of the DLX1414 and the LP. The typical data output hold time is only 30 ns for DBE=02 timing; two inverters in the DBE line are added to increase the data output hold time for compatibility with the 50 ns minimum spec of the DLX1414. Figure 9. Mapped interface
Reset Int H old Wait Optional Bu ffers
Por t A 0-6
A0 A1 A2 A3
Po r t B
A B 7442 C D
3 2 1 0
WR
8255
Figure 8 illustrates a 16-character display with an 8080 system using the 8255 programmable peripheral interface I/O device. The following program will display a simple 16 character message using this interface. Program for 16-Character Message
INT: MVI A,80H OUT CONTROLMVI B,00H LXI H, TABLE MOV A,M OUT PORTA MOV A, B CALL DSPWT INX H INR B MVI A, 10H CMP B JNZ DISP1 HALT DSPWT: ORI F0H OUT PORTB ANI 7FH OUT PORTB ORI F0H OUT PORTB RET TABLE: DL DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB ;CONTROL DATA MODE 0 ;LOAD CONTROL REGISTER ;SET COUNTER =0 ;SET TABLE ADDRESS ;MOVE TABLE DATA TO ACCUMULATOR ;LOAD DATA PORT ;LOAD ADDRESS AND CONTROL ;INCREMENT TABLE ADDRESS ;INCREMENT COUNTER ;SET # OF DIGITS ;16 CHARACTERS ? ;END OF PROGRAM ;SET CONTROL BITS OFF ;LOAD CONTROL ;SET WRITE BIT ON ;LOAD WRITE ;SET WRITE BIT OFF ;LOAD CONTROL ;0C3H ;0C9H ;0D4H ;0D3H ;0C1H ;0D4H ;0CEH ;0C1H ;0C6H ;0A0H ;0D3H ;0D4H ;0C8H ;0C7H ;0C9H ;0CCH
Address 8080 Z80 6502 D ata
Address
Data
OSC
Control
DISP: DISP1:
D isplay D isplay D isplay D isplay D15 D0
Data 0-6 A0 A1
0 A 1 B Decoder 2 C 3 D
A2 A3 Dis play Select WR
Figure 10. Gating the write pulse
Reset NMI Halt IRQ TSC
Data 6800 Address 01 02 DBE
Data Address
H1 H2
Clock Driver
BA VMA R/W Decoder
Display
Display
Display
Display A0, A1 D0-D7
CE CE
Conclusion Although other manufacturers' products are used in examples, this application note does not imply specific endorsement, or recommendation or warranty of other manufacturer's products by Infineon / OSRAM. The interface schemes shown demonstrate the simplicity of using the DLX1414 with microprocessors. The slight differences encountered with different microprocessors to interface with the DLX1414 are similar to those encountered when using different RAMs The techniques used in the examples were shown for their generality. The user will undoubtedly invent other schemes to optimize his particular system to its requirements.
Appnote 15
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
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May 31, 2000-12

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